Veyron

Platform Architecture

Secure and Scalable Memory Architecture

Robust Memory Management and Privilege Isolation

Ventana’s Veyron V2 platform implements advanced virtual memory capabilities using the RISC-V Sv39 and Sv48 page-based virtual memory schemes. These provide 39-bit and 48-bit virtual address spaces respectively, enabling support for large memory configurations typical in data center and edge environments. Each core integrates a high-performance MMU with per-core TLBs, minimizing latency on address translation and supporting fast context switching in multi-tenant systems.

Enhanced Physical Memory Protection (ePMP) for Secure Systems

In addition to standard virtual memory, Ventana CPUs support Enhanced Physical Memory Protection (ePMP), which extends the original RISC-V PMP (Physical Memory Protection) specification to provide fine-grained control over physical memory access. ePMP enforces execute/read/write permissions across privilege levels and supports dynamic reconfiguration of memory regions. While especially useful in bare-metal and real-time deployments, its utility goes far beyond those environments. ePMP plays a key role in secure boot flows, sandboxing trusted execution environments, and hardening hypervisors. It enables memory isolation even after virtual memory is enabled—helping enforce zero-trust security principles and defend against privilege escalation. ePMP also supports hybrid systems with both MMU and non-MMU components, delivering consistent, hardware-enforced access controls from early boot through full OS runtime.

System-Level Integration for Comprehensive Isolation

Ventana’s memory protection features are tightly integrated with other system-level security and isolation mechanisms, including the IOMMU. This enables device-level protection by preventing misbehaving or compromised peripherals from accessing unauthorized memory through DMA. Whether running Linux in virtualized environments or low-latency workloads on bare-metal, the combination of MMU and ePMP ensures secure, scalable, and predictable memory behavior across all use cases.

IOMMU for Virtualization, Security, and Accelerated Compute

The Input-Output Memory Management Unit (IOMMU) is a foundational system IP block for enabling virtualization, ensuring security, and supporting high-performance accelerator integration. It acts as the device-side equivalent to the CPU’s MMU, safeguarding memory by enforcing access permissions for DMA-capable devices. Whether in a virtualized data center environment or a high-assurance embedded system, the IOMMU prevents unauthorized memory access and enables device isolation—critical for modern multi-tenant and multi-core platforms. Ventana’s IOMMU IP is fully aligned with the ratified RISC-V IOMMU v1.0 standard. Designed for 64-bit RISC-V systems, it supports two-stage address translation and Shared Virtual Memory (SVM), enabling efficient direct device assignment and seamless integration with modern OS and hypervisor stacks. The implementation is optimized for low-latency translation, robust access control, and full compliance with interrupt handling and virtualization requirements across cloud and edge workloads.

Key features of Ventana’s IOMMU include:

Full compliance with RISC-V IOMMU v1.0 specification
Two-stage address translation (GVA→GPA→HPA)
Shared Virtual Memory (SVM) with support for page-based and fine-grain access
Hardware support for Sv39 and Sv48 address translation schemes
Address translation cache architecture with multi-level translation lookaside buffers (TLBs)
MSI (Message-Signaled Interrupts) delivery support, including compatibility with RISC-V AIA
Integrated 48-entry PMA and 64-entry PMP for fine-grained memory access enforcement
PCIe ATS (Address Translation Services) and PRI (Page Request Interface) compatibility
Device-level fault reporting, interrupt remapping, and page fault isolation
Seamless integration with Ventana CPUs and system IP, including trace and debug infrastructure

Together, these features allow accelerators and peripherals to operate within a unified virtual memory environment, supporting low-overhead compute offload and improved security posture. The IOMMU also serves as a key building block for scalable chiplet systems, enabling safe and flexible composition of heterogeneous compute domains.

Advanced Interrupt Architecture

Ventana’s processors implement the RISC-V Advanced Interrupt Architecture (AIA), which modernizes interrupt handling by eliminating traditional sideband signals in favor of scalable, memory-mapped message-signaled interrupts (MSIs). This shift allows for simpler and more efficient designs, especially as core counts grow. Each Ventana Veyron features its own Incoming MSI Controller (IMSIC), handling prioritization, masking, and routing of external interrupts—fully supporting machine (M), hypervisor (HS), and virtual supervisor (VS) privilege levels.

To complement this, Ventana provides an Advanced Platform-Level Interrupt Controller (APLIC) for systems that still require support for legacy wired interrupts. The APLIC module converts these wired signals into MSIs, ensuring smooth interoperability in mixed environments. Additionally, memory-mapped interrupt registers via RegBus and software-generated interrupts are supported, along with virtualization-ready features like interrupt isolation per guest VM.

Ventana’s AIA implementation is built for enterprise-grade reliability and extensibility. It supports IOMMU-related interrupts and aligns with modern RISC-V practices. The result is a flexible and secure foundation that scales cleanly from intelligent edge platforms to cloud-scale processors.

Virtualization and RISC-V

Virtualization allows multiple operating systems or workloads to run securely and efficiently on a shared compute platform. In modern data centers, hypervisors enable partitioning, isolation, and dynamic scaling—powering use cases from cloud hosting and dev/test environments to edge computing and software-defined infrastructure. Traditional x86 and Arm platforms rely on hardware extensions to support virtualization of both compute and I/O, enabling high performance through direct device assignment and interrupt remapping.

RISC-V now offers a competitive virtualization foundation through the ratified H-extension, which introduces new privilege modes, virtualized control registers (vCSRs), and two-stage address translation. Ventana’s Veyron CPUs implement full hardware support for the RISC-V H-extension, enabling high-performance virtualization of guest operating systems with support for IOMMU-based device isolation, interrupt virtualization, and hypervisor-managed memory protection. These features allow customers to build Type 1 and Type 2 hypervisors with near-native performance.

Ventana is also at the forefront of nested virtualization support—enabling virtual machines to themselves host additional VMs. This capability is critical for modern cloud and container platforms, developer sandboxing, and real-world simulation environments. Combined with robust platform IP such as AIA, APLIC, and IOMMU, Ventana’s RISC-V platform offers a scalable, standards-aligned virtualization foundation ready for enterprise and cloud-scale deployment.

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