RISC-V CPU IP, Chiplets and Platforms



Veyron V1

Ventana's first generation RISC-V high performance CPU is targeted at data center, edge, and other general computing applications. The configurable CPU cluster can be integrated as IP within an SoC, delivered as an optimized compute chiplet, or within an ASSP/CSSP SiP standard product.

Veyron is a server-class CPU, meeting all the requirements to run virtualized cloud-native workloads and adhering to robust data center requirements. The V1 IP portfolio includes key RISC-V system IP components such as an IOMMU, and its interface is compliant to common AMBA protocol standards, such that complete high performance system solutions can be easily integrated with available third-party IP.



  • Aggressive eight-wide deep out-of-order pipeline
  • Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2
  • Large high-bandwidth cluster-level shared L3 cache (up to 48MB)
  • Large BTB/TLB structures important for data center applications
  • AMBA CHI 256-bit system interface


Perf/W Optimization

  • Configurable TDP to define the desired performance-power profile
  • Turbo profile management to maximize performance within a TDP
  • Cluster-level and per-core digital power models to control turbo behavior



  • Full architectural support for virtualized workloads
  • Comprehensive RAS (ECC, error logging/scrubbing, data poisoning)
  • Patented new microarchitecture resilient to side-channel attacks
  • Top-down performance analysis methodology for software optimization


Implementation Details

  • Configurable as 1/2/4/8/16-core clusters, 0.75/1.5/3MB L3 slice per core
  • Highly portable design with no custom macros or RAMs dependencies

Rapid Deployment

  • Chiplets logically interface as an AMBA CHI RN-F CPU cluster
  • D2D link optimized for ultra-low latency, critical to CPU performance
  • D2D PHY adheres to the ODSA BoW (Bunch of Wires) standard, UCIe will be supported in the future as it matures
  • CPX System IP
    Ventana provides the V1 CPX (Cluster Proxy) IP for the companion IO Hub SoC integration to seamlessly interface to V1 compute chiplets. Interface profile details can be found through Open Compute ODSA:
    Ventana Veyron V1 ODSA Interface Profile
Product (System in Package)

Contact us to explore the following ASSP solutions

  • Accelerated DPUs
  • Accelerated 5G Open RAN platforms
  • Servers and edge compute platforms

Have a specific need? Contact us to see how Ventana’s vast partner ecosystem can help assemble a CSSP to meet your needs.


We are looking to fill multiple technical R&D positions to continue the development of innovative RISC-V processors and subsystems