Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V simplifying system principles.
RISC-V AIA (Advanced Interrupt Architecture) builds upon PCIe MSI (Message-Signaling Interrupts) to reduce the complexity of the interrupt implementation. Using memory mapped transactions removes the need for specialized interrupt protocols and sideband interrupt signaling networks. Ventana CPUs include the AIA IMSIG (Incoming Message- Signaled Interrupt Controller) function within the CPU cluster to process interrupts within each CPU core. The APLIC IP can be used if there are wired interrupts that need to be converted to MSI transactions.
Debug & Trace
RISC-V debug & trace utilizes a memory mapped architecture to remove the need for specialized protocols and sideband trace buses. CPU traces are sent to main memory with a timestamp using a unified system timebase (mtime) established at startup. CPU and system traces can then be read out from memory over any high-speed IO interface and combined using the timestamps to stitch together the system context.
Memory Protection & Translation
Ventana utilizes RISC-V architecture features that allows protection at the source of a transaction, compared to a destination approach as found in some common legacy architectures. Source side allows a richer and more fine grain set of protection constructs compared to a destination approach. The ePMP (enhanced Physical Memory Protection) functionality is implemented within Ventana’s CPU for CPU- based transitions, while the IOMMU protects against device-based transactions.